In the earlier European patent application 09012023.9 the basic problems which exist during alignment are described on pages 1 to 3.
Due to the 3D technology which is becoming more and more important in combination with progressing miniaturization, it is becoming more and more important in bond processes to carry out a correct alignment process, especially coupled with a so-called pre-bonding step which connects the wafers to one another by means of a separable connection prior to the actual bond process. This is important mainly in applications in which alignment accuracies of better than 2 μm for all locations on the wafer are desired. The importance and requirements for accuracy of the alignment technology and of the pre-bonding process increase greatly for desired accuracies less than 1 μm, especially less than 0.5 μm or less than 0.25 μm.
Based on the fact that the structures are becoming smaller and smaller, but the wafers at the same time are becoming larger and larger, there can be structures which are very well aligned to one another in the vicinity of alignment marks, while at other positions of the wafer the structures have not been correctly or at least not optimally joined to one another. In order to optimally join the structures on both sides of the wafer to one another, very complex alignment technologies coupled to very well monitored and optimized bonding technologies, especially pre-bonding technologies, are being developed.
Current technology is intended to record some alignment marks on one side of two wafers at a time and to align the two wafers afterward using these alignment marks and to bond them. Here several problems arise, depending on the respective technology which is used for the alignment.
The applicant with European application EP 09012023.9 has already filed a method using which it is possible to measure the entire surface of a wafer in order to obtain information about the positions of the structures on the surface of each wafer.
The object of this invention is to develop a generic device or a generic method such that higher detection relating especially to the entire surface of the wafer for more exact alignment is achieved and errors in the detection of positions or later alignment are minimized. In addition the object of this invention is to increase the throughput in the detection of the positions and the alignment of wafers.
This object is achieved with the features of Claims 1, 4, and 8. Advantageous developments of the invention are given in the dependent claims. All combinations of at least two of the features given in the specification, the claims and/or the figures also fall within the framework of the invention. At the given value ranges, values within the indicated limits will also be disclosed as boundary values and will be claimed in any combination.